ABOUT THE CONFERENCE

 

FPGA is our passion.

We are changing the world through this. So you can!
Join the hackathon we organize in Kraków to learn more about the technology gaining more and more popularity!

Sharing this passion is the reason why we decided to create this conference.

FPGA technology is one of the foundations for the revolutionary projects like fast telecommunication or autonomous cars.

Thanks to the fast data processing and an ability to work on many resources, FPGA is a key in banking and insurance sector (acceleration of calculations and risk analysis based on data) or stock operations.

And that’s not all!

The mission of the event is to spread the knowledge of FPGA topics, meeting interesting guests and common networking.

 

What do you get at the Conference?

• knowledge of the latest FPGA challenges and solutions

• meetings with inspiring specialists and building a social and business relationship

• attending interesting lectures

• the opportunity to share your knowledge with FPGA specialists and enthusiasts

 

How can you join the event?

Registration for the Hackathon is already closed but you can sign up for the Conference till the last moment.

ABOUT THE HACKATHON

Imagine you’re sitting in a spaceship, ready for the greatest adventure of your life – the Mission to Mars.

There is an overwhelming darkness around you, from time to time you only see the flash of a burning star.

But suddenly something changes. In the distance you see the masses coming, thousands of meteors flying straight at you.

In this chaos, you try to save the most precious thing, your ship.
But the only thing that can help you is the meteor coordinates from the mysterious satellites.

Your radio, based on FPGA technology, can’t keep up with their readings, gets lost in interpretation.

You only have 24 hours to create a key and read the clues correctly.

Do you dare to take that step?

Will you be among the hundreds of daredevils who will save the Mission to Mars?

 

What do you need?

A team of 2-3 people ready for the challenge (individual registration will not be possible).
If you don’t have a team contact us and we will help!

Programming skills with FPGA background (even if it’s just a little, it is good enough) / Technical skills in FPGA-related areas.

 

What do we provide?

HW: development board per team with USB programmer cable and power supplier (Cyclone V GX Starter Kit),

Access to selected FPGA Design and Verification related tools under provided licenses:

 

• MATLAB & Simulink from MathWorks,

 

• Questa Simulator from Mentor Graphics,

 

• OneSpin 360™ Formal Verification Tools from OneSpin,

 

• Quartus from Intel,

 

• Riviera-PRO from Aldec,

 

What are you fighting for?

In addition to the enormous knowledge you gain, we guarantee you great fun with the same enthusiasts.

As well as material prizes received from sponsors and event partners.

Prize list will be published soon.

At this moment value of all prizes is 16 000 PLN.

 

How can you join the event?

The only thing you need to do, to become a hackathon participant is to register your team or yourself by filling the form.

Minimum team size which will be accepted during registration is 2 members (then at least one person will be added from individual subscriptions).

Registration for the Hackathon is already closed. You can still register for the Conference instead!

 

Are you interested, but want to know more?

Check the FAQ at first. If there’s no answer for your question, please feel free to contact us with an e-mail:

[email protected]

EVENT SCHEDULE

CONFERENCE | 20 November 2020
Due to the change in the form of the conference, all hours are subject to change
8:45 - 9:00 CET Opening ceremony

Coverage Driven Verification

Speaker: Stefan Bauer (Account Technology Manager – Mentor, a Siemens Business)

Q&A: Juho Järvinen (Mentor, a Siemens Business)

9:00 – 9:45 CET

Read More

9:45 - 9:55 CET Short break

Targeting Signal Processing Algorithms to Systems-on-FPGA

Speaker: Werner Bachhuber (MathWorks)
9:55 – 10:40 CET

Read More

10:40 - 10:45 CET Short break

Refactoring SystemVerilog code

Speaker: Michał Kahl (Nokia)
10:45 – 11:15 CET

Read More

11:15 - 11:20 CET Short break

Clock Domain Crossing - Design Techniques

Speaker: Sławek Grabowski (Aldec)
11:20 – 12:05 CET

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12:05 - 12:45 CET Lunch break

IEEE presentation

12:45 – 13:00 CET

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FPGA accelerators for compute: Intel PAC

Speaker: Pawel Olejniczak (Intel)
13:00 – 13:30 CET

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13:30 - 13:35 CET Short break

ASIC vs FPGA (Selection criteria, Compatibility, Porting challenges)

Speaker: Maciej Wojtowicz (Nokia)

13:35 – 14:20 CET

Read More

14:20 - 14:25 CET Short break

The Mars Chronicle: FPGA Verification Platform Saves the Day

Speaker: Vladislav Palfy (OneSpin)
14:25 – 15:10 CET

Read More

15:10 - 15:15 CET Short break

P4 and Intel PAC N3000 - make FPGA networking deployment faster

Speaker: Miroslaw Walukiewicz (Intel)

15:15 – 16:00 CET

Read More

16:00 - 16:15 CET Conference closure
HACKATHON | 21-22 November 2020
11:00 CET Hackathon Opening and Task presentation

Official Hackathon start

21 November – 11:30am CET

Official Hackathon finish

22 November – 11:30am CET

Results presentation

22 November – 12:00pm CET

SPEAKERS

Vladislav Palfy

(OneSpin)

Vladislav Palfy, Director of Application Engineering at OneSpin Solutions, has over 10 years of experience in EDA in field application engineering and management. Vladislav joined the team in 2015 and is responsible for leading a multinational team of engineers that support OneSpin’s existing and future customers.

Vladislav has deep technical knowledge from working as a field application engineer and has been keeping his technical skills sharp throughout his transition into management. He has a passion for driving customers to success and cultivating the support philosophy within his team that sets OneSpin apart in the EDA world. Prior to joining the team at OneSpin, Vladislav was a team lead and methodology engineer at Methods2Business.

Vladislav holds a Master of Science in Electrical and Computer Engineering from the University of Novi Sad. When not on a customer visit, he devotes his time to family, sports, and volunteering with a charity organization.

Michał Kahl

(Nokia)

Michał has worked in Nokia and Motorola for over 13 years. During his career as an FPGA engineer, he learned to appreciate good coding practices in RTL design.

Graduate of Jagiellonian University (physics) and AGH University of Science and Technology (electronics and telecommunications), lecturer in Nokia FPGA Academy, co-author of two publications on nonlinear models in curved spacetimes.

Apart from programmable devices, his professional interests cover information theory,  functional programming and machine learning. Among his scientific interests are nonlinear differential equations and general relativity.

Werner Bachhuber

(MathWorks)

Dr.-Ing. Werner Bachhuber holds a PhD equivalent degree from the Institute for Integrated Circuits at the Technical University of Munich/Germany.

Before joining MathWorks he worked as a Senior Field Application Engineer for an FPGA vendor. Prior to this role he held various positions in ASIC and ASSP development focused on high data rate wireline communication systems.

His experience covers all steps in the design and verification flow from the requirement specification down to the physical implementation in silicon.

Maciej Wojtowicz

(Nokia)

Maciej Wojtowicz had worked at Cadence Design System for the last 8 years (including Evatronix acquisition) and got silicon proven experience in designing complex digital controllers, modules and devices using best in class project organization techniques (from planning phase to completion).

He has had deep ASIC flow experience (Verilog for Synthesis, STA, P&R, CDC, LEC, Lint, DfT, ATPG etc.) including quality management for all these flows. He has had experience in being project Design Lead and making business unit impacting decisions for ASIC products.

During his time at Cadence, he was dealing with complex and challenging customer issues by meetings, technical calls, debug sessions, exchanging e-mails and was working closely with cross-functional teams including MKT/Sales on how to overcome issues and plan the roadmap.

He has got deep experience in deploying ISO26262 requirements for Semiconductors resulting in getting ASIL-B Certification for two projects and holds proven records of improving and automation of global company automotive methodology.

At Nokia, Maciej is working on critical 5G design components and cross-functional quality program for design entry development.

Juho Järvinen

(Mentor, a Siemens Business)

Juho Järvinen is an application engineer for design and verification tools at Mentor Graphics and holds a M.Sc. degree from Helsinki University of Technology (Telecommunications & Electronics).

Juho has a 12+ year experience from ASIC/FPGA design & verification lead positions of IP router forwarding chips in mobile backhaul products. Juho’s skills include deep knowledge of UVM methodology in verification and formal tools, methodologies and CDC.

In addition to passion for digital design and verification, family, music and sports such as triathlon & cycling keep him busy.

FPGA Hackathon Krakow lecturer Slawek Grabowski

Sławek Grabowski

(Aldec)

Slawek is Engineering Manager at Aldec Hardware Division. Graduate from AGH University of Science and Technology in Krakow, Poland 1998.

Slawek has over 22 years of experience in the area of FPGA design and verification and ASIC emulation. He patented technologies for mapping ASIC designs into multiple FPGAs.

He is one of the main architects of Aldec HES emulation and prototyping systems. Slawek has been involved in verification of over 50 avionics designs where quality and robustness are crucial for flights safety.

Mirosław Walukiewicz

(Intel)

Miroslaw Walukiewicz is a Solution Architect in Intel programmable Solution Group working on defining customer use-cases with FPGA.

He works in area of network processing pipelines in HW connected efficiently with SW stack for management.

He has 27 years of experience in networking designs.

IEEE

(Institute of Electrical and Electronics Engineers)

IEEE and its members inspire a global community to innovate for a better tomorrow through highly cited publications, conferences, technology standards, and professional and educational activities. IEEE is the trusted “voice” for engineering, computing, and technology information around the globe. Our Mission and core purpose is to foster technological innovation and excellence for the benefit of humanity. IEEE will be essential to the global technical community and to technical professionals everywhere, and be universally recognized for the contributions of technology and of technical professionals in improving global conditions.

 

Our goals are to:

• Drive global innovation through broad collaboration and the sharing of knowledge

• Enhance public understanding of engineering and technology and pursue standards for their practical application

• Be a trusted source of educational services and resources to support life-long learning

• Provide opportunities for career and professional development

• Inspire a worldwide audience by building communities that advance technical interests, inform public policy, and expand knowledge for the benefit of humanity

Paweł Olejniczak

(Intel)

Paweł is an experienced SoC design engineer with a demonstrated history of working in the semiconductors industry for over 12 years. He has familiarity with ASIC design, pre-silicon verification and emulation on FPGA and hybrid platforms. Before joining Intel he had worked as a designer for original device manufacturers as well as high grade communication equipment providers. Today he works as part of system solution engineering, engaging closely with clients, to build solutions that solve crucial problems customers face.

In spare time he is an eager supporter of light electric vehicles for everyone – including building those from scratch.

FREQUENTLY ASKED QUESTIONS

About Hack into Mars Event

What is the FPGA Hackathon and Conference - Hack into Mars?

Social coding contest where FPGA developers collaborate to solve given tasks and compete for prizes. Hackathon will be preceded by FPGA subject related Conference.

This Event is also a great networking opportunity! 

Who is this Event for?

The Conference is for everyone interested in FPGA subject. 

The Hackathon is for students and professionals of any engineering and technology career, enthusiasts of microcontrollers, FPGAs, programming and electronics in general.  

If you would like to have your first experience solving basic problems of FPGA or you are already experienced and you want to challenge your skills on FPGA, then this hackathon is for you! 

How much does it cost?

FREE. Registration and participation in both Hackathon and Conference is free of charge.

When and where?

20-22 October 2020.

Considering safety of Participants we have decided to switch formula of FPGA Conference and Hackathon to online mode. The whole event will be held on dedicated Discord server, which You can find under the link, send to you in the mail after registration.

Teams

How many people should be in a Team?

Team for FPGA Hackathon should consist of 2-3 people. Individual registration is not possible.

There are no Teams for Conference 😉

Where to register?

Registration for the Hackathon is closed. But you can still sign up for the Conference!

What if I want to take part in Hackathon but I don’t have the team?

Don’t wait and contact us as soon as possible! In such case you will be teamed with other persons.

Task

What is a Task?

The Task will be revealed at the beginning of the Hackathon.

How the Teams will be judged?

Submitted Quartus project should allow bitfile generation. Generated bitfile will be automatically verified at setup containing two Cyclon V kits by using script created in Python3. Script result is the measurement of required performance factor (announced during Hackathon task presentation) which is base for winners ranking. Organizer will check the best 3 solutions manually to confirm that configuration files are not modified by participants. In case of proven modifications team will be disqualified.

How much time will be available to complete the Task?

The team must complete the task in 24 hours.

Are there going to be some mentors to help me with the Task?

Yes, during the whole event there will be a group of Mentors on the Discord server, willing to help you in struggle. More information about that will be provided on the first day of Hackathon.

How can I get access to the development board and FPGA Design and Verification tools provided for the participants by the organizers?

We know, that completing the Task without dedicated tools and devices would be impossible. That’s why we give your team access to related tools under provided licenses: MATLAB & Simulink from Mathworks, Questa Simulator from Mentor Graphics, OneSpin360TM Formal Verification tools from OneSpin, Quartus from Intel and Active-HDL from Aldec.

Also, there will be possibility to use development board with USB programmer cable and power supplier (Cyclone V GX Starter Kit). More information about access will be send to the participants soon enough.

Where should I submit my solution?

With given assets, participants relying on their knowledge and chosen technology, are supposed to submit solution on assigned GitLab repository for task announced at Hackathon first day. Solution should contain whole Quartus project needed for bitfile generation (including all configuration files and HDL code).

How am I going to present my solution?

The winners will be asked to present their solution to the organizers.

Organizational Information

What is the language of the contest?

The Hackathon and The Conference will be held in English.

What should I prepare?

Prepare your laptop, mobile phone, wearable computing devices and whatever technology inspires you. Don’t forget about your chargers and Internet connection. Make sure that you will feel comfortable during intense hacking. Above all, prepare your energy and your brain!

Additionally you will need to register on Discord. Be aware, that you need to have active account on Discord. You don’t have to download the Discord to your Desktop – browser version is also enough.

Do I have to stay online the whole time?

Competitors don’t have to stay online to be eligible to win, but we strongly encourage to stay up the whole 22 hours. At least one team member should be online at the results presentation. Note, in case your Team wins competition, your prize will be shipped to the address you have provided in Registration form.

What will be provided during the Hackathon?

There will be Mentors willing to help you, FPGA boards with online access and virtual machines with SW delivered by our Sponsors, required to complete the tasks.

More info about provided tools, boards and contact with Mentors will be provided on the first day of Hackathon, on the event’s Discord server.

Will there be prizes?

You bet!

1st place – Intel® NUC Mini PC + Withings Move Basics

2nd place – Terasic DE10-Nano Kit development kit + Withings Move Basic

3rd place – Movidius stick + Withings Move Basic

Besides, there will be “thank you” pack sent after the Event to active Competitors of Hackathon.

To equip fearless Mars explorers with the knowledge and experience they need to succeed in future expeditions across the galaxy, OneSpin is pleased to award a special OneSpin Formal Verification Training to the winning Hackathon team.

This one-day training session from OneSpin’s IC integrity experts will include:

  • Overview of verification methodology and the advantages of formal verification
  • Crash-course in SystemVerilog Assertions (SVA)
  • Tips on how to leverage OneSpin’s tools and apps for maximum success

A representative from OneSpin will connect with the winners after the Hackathon to schedule the session. Each member of the winning team may also invite one friend or colleague to attend the training—because success is sweetest when shared!

How will be prizes delivered to winners?

Prizes will be sent to the address provided during the registration.

Where do I sign up?

Note, there are separate registration forms for the Conference and the Hackathon.

Registration for Conference is individual, while registration for Hackathon should be done by one member of the Team (Leader).

Team Leader have to register whole Team of 2-3 members by providing: name, surname and e-mail address of each of Team members. Additionally Team Leader have to provide his telephone number. Each Team member will receive email with link to confirm participation and give appropriate information and consents. Team will be successfully registered only after receiving required consents confirmation from all Team members.

After successfully filled registration form, each Team member will receive e-mail with  further instructions.

What if I have more questions?

Email us or write to us on Facebook and let us know how we can help. 

You can also find more details in FPGA Hackathon and Conference Terms and Regulations which will be published closer to the Event

ORGANIZERS

PATRONS

SPONSORS

SUPPORTERS