5th edition of the FPGA Hackathon has come to the end!

Congratulations to the Winners:

 

       1st place: 

                 Kuźnia Rdzeni

 

       2nd place: 

                 Parallel Failure

 

       3rd place: 

                 BigDataSmallMemory

 

 

Thank you All for a participation.
See you next year!!!

Welcome to the FPGA Hackathon Official Site!

Join us online! FPGA Hackathon 2024 Live Stream from Kraków:

2024 Main Theme
Humanity has always considered the Moon as a source of mysteries, inspiration, and fascination as well as a symbol of challenges, opportunities, and dreams of the distant future in space. It indeed is a gateway to the exploration of the Solar System, and it was already used in this role when humanity intended to settle on Mars.
After recent successes on the Red Planet, scientists, engineers, and space developers have gained enormous experience that could be used in a more ambitious project – the construction of a lunar metropolis, which is to become not just a sign of technological progress, but also a powerful impetus for scientific research and space exploration.
Constructors who will take part in the creation of the lunar metropolis will face numerous challenges, both technical and organizational. Work on this project requires not only advanced technology, but also international cooperation and the involvement of many fields of both the science and space industry.
Once again, the engineers decided to use a technology that did not disappoint them – FPGA. These systems allow flexible design and adaptation of systems to specific needs and changing conditions in space. Their ability to process data in real time and adapt to different tasks is especially valuable in difficult space environments, such as the one on the Moon.
A competition was announced to select teams that will be part of the future constructors of the lunar metropolis. As part of the competition, teams will face a series of tasks in which they will have to use FPGA technology to solve various challenges related to the implementation of this ambitious project. The time for its completion will be 24 hours.
The choice of the place to build the metropolis was not chosen randomly – as imply reliable sources. 
Apart from participating in the competition, could teams of engineers help answer the question whether humanity is alone in space?
2024 hardware hero
The hardware hero of this year’s FPGA Hackathon is… Kria KV260! Kria KV260 is a starter kit manufactured by AMD that shines as a low-cost board for all FPGA enthusiasts.  As all Kria SOMs, it is equipped with a custom-built Zynq UltraScale+ processor which proofs useful when heading for various goals in diverse applications fields such as robotics, signal processing and vision AI.
Prizes

Apart from enormous knowledge gain, combined with eternal honor and glory, for winners we will provide in-kind prizes with a possibility of choice (though slightly limited). This way you don’t need to worry about winning something you already own! 

Each team member will have the opportunity to choose one of the prizes (exact models will be presented for selection by the winners on the day of the hackathon):

 

1st place:  Prize of value approx. 3 000.00 PLN per Team Member

 

2nd place: Prize of value approx. 2 000.00 PLN per Team Member

 

3rd place:  Prize of value approx. 1 000.00 PLN per Team Member

Hackathon Schedule

Saturday - April 20, 2024

check

9:30 – 10:45 AM CET

Check-In at Krakow Technology Park

verification of registered participants

lte

9:30 – 11:00 AM CET

Series of short talks and presentations

-Can a cellular network work on the Moon? [Nokia]
-Game Industry: behind the scenes [KPT]

open

11:00 AM CET

Opening Ceremony

FPGA Hackathon 2024 opening and task presentation

lift-off

12:00 PM CET

The Lift-Off!

the official start of the hacking

ikonka_blue

Available since 12:00 PM CET

Attractions

-snacks
-ice creams from Good Lood
-VR gaming zone
-Moon Discovery Tournament - official FPGA Hackathon game (PC)
-de-stress activities: slackline, jugglery, and more...

lunch (2)

3:00 PM CET

Lunch

diverse and delicious meal

pizza1

7:00 – 11:00 PM  CET

Supper

hot & tasty pizza is served

fire

10:30 PM  CET

FIRESHOW

unique show performed by talented artists

Sunday - April 21, 2024

lunch (2)

7:00  – 10:00 AM CET

Breakfast

healthy, juicy and nutritious meal

lte

10:30 AM – 12:30 PM CET

Can a cellular network work on the Moon?

short presentations of Nokia's project

finish

12:00 PM CET

The Landing

end of the hacking

closing

 12:30 PM

Hackathon Closure Ceremony

winners presentation of
- FPGA Hackathon 2024
- mini tournaments

Saturday - April 20, 2024

check

9:30 – 10:45 AM CET

Check-In on Discord

verification of registered participants via voice channel on Discord

open

11:00 AM CET

Opening Ceremony

stream from KPT: FPGA Hackathon 2024 opening and task presentation

lift-off

12:00 PM CET

The Lift-Off!

the official start of the hacking

Sunday - April 21, 2024

finish

12:00 PM CET

The Landing

end of the hacking

closing

 12:30 PM

Hackathon Closure Ceremony

stream from KPT: winners presentation of
- FPGA Hackathon 2024
- mini tournaments

Location

The fifth edition of the FPGA Hackathon is organized on April 20-21, 2024 in a hybrid manner.
You can participate in two ways:

          onsite – visit us in Krakow Technology Park

          online – join us from all around the world

 We are looking forward to meeting you all!
Frequently Asked Questions

What is the FPGA Hackathon? 
It’s a social coding contest where FPGA developers collaborate to solve given tasks and compete for prizes. This Event is also a great networking opportunity! 

 

Who is this Event for? 

The Hackathon is for students and professionals of any engineering and technology career, enthusiasts of microcontrollers, FPGAs, programming and electronics in general.  

If you would like to have your first experience solving basic problems of FPGA or you are already experienced and you want to challenge your skills on FPGA, then this hackathon is for you! 

 

 

How much does it cost? 

FREE. Registration and participation in both Hackathon is free of charge. 

 

 

When and where? 

April 20-21, 2024 Krakow Technology Park and online

How many people should be in a Team? 

The Team should consist of 2-3 people.


I don’t have a Team, what now? 

Unfortunately, we do not accept individual registrations this year. You must register with at least one other person.


What should we do when one of our Team Members will not be able to participate in the Hackathon? Can the rest of our Team still participate? 

Yes, you can still participate in smaller team, but you have to inform Organizers about every personal changes in your team.


How to register other Team Members?
Everyone must sign up separately. If you have a team every Member must provide the same ‘team name’ in the appropriate field in the registration form.

What is a task? 

The detail regarding the task will be provided on Hackathon start day during the Event.  


How will Teams be judged?

Judging criteria will be described in separate documents on Hackathon start day during the Event

What is the language of the contest? 

The Hackathon is held in English.  


What should I prepare? 

Prepare your laptop, mobile phone, wearable computing devices and whatever technology inspires you. Check your Internet access. Make sure that you will feel comfortable during intense hacking. 


Do I have to stay the whole time during Hackathon? 
Competitors don’t have to stay overnight to be eligible to win,  but we strongly encourage to stay the whole 24h. At least one team member must be present at the results presentation to show their Team’s work effects. 


What will be provided during Hackathon?

FPGA boards, virtual machines with SW delivered by our Sponsors required to fill the tasks, instructions, all needed credentials and links. There will also be Mentors who will help you in troubles.
At the in-person Event Organizers will provide many attractions. 


Will there be prizes? 

Winners will receive fantastic prizes, while each stationary participant will also receive a variety of gadgets.


Where do Isign up? 

Registration links are available on the Events’ website. Remember about deadlines!


What if I have more questions? 

Email us and let us know how we can help. You can also find more details in Terms and Regulations. 

Photo gallery
2023 Official Aftermovie
2022 Official Aftermovie

FPGAs in Space Communication for Dummies

Michał Kuklewski, Thales Alenia Space

Due to their versatility and configurability, Field Programmable Gate Arrays (FPGAs) continue to be a very attractive choice in many places instead of purpose build ASICs. Space applications – in low or high orbit or even on other planets – are one of them. Depending on mission conditions or requirements, there is the possibility of using commercial off-the-shelf (COTS) devices in contrast to radiation-hardened FPGAs with built-in protection by technology. The use of any of these has associated implications and requires appropriate protection to assure reliability and achieve its function. 

As an example, the application is terminals for space communication – either between a ground station and a satellite or between satellites.  To achieve it, space agencies are following CCSDS standards, thus enabling the interconnection of different systems, while minimizing risks during missions, maximizing success rate and achieving interoperability. 

This presentation features a compilation of information from the ECSS standards and handbooks for protecting FPGAs against the effects of space radiation and an introductory description of CCSDS communication standards that allow communication with satellites. 

Mars – the most fascinating target for the space exploration
 – the technological challenge
 

Piotr Orleański DSc, CBK PAN Warszawa

The lecture will present the summary of the different space missions to Mars with the special attention on the technological challenges (environment conditions, available power, communication issues, components reliability). The more detailed information will be given on the three missions (Mars Express, ExoMars and InSight) where Polish engineers have been involved in design and manufacturing of the space instruments. 

Sending humans to Mars: a beginner’s guide

Jakub Hajkuś, To Jakiś Kosmos

So, you’re about to go to Mars? That’s great! Pack your toothbrush and lunch box. Your spacecraft isn’t ready? Oh, You don’t have one yet. Let’s try to do something about it. It’s not easy to get from Earth to Mars, but I’ll walk you through the process. Leaving our blue planet, cruising and landing on Mars require creativity. I will introduce you to a few options from which you can choose. Better clear your schedule as the journey usually takes several months. Warm clothes and sunscreen are a must. Being in space or on Mars can hardly be called a perfect holiday. I almost forgot! Consult with your doctor about whether you may be exposed to strong cosmic rays. Don’t worry, you are in good hands!

The Hitchhiker’s Guide to the FPGAs.
How to make FPGAs work in space

Adam Milik DSc, ALDEC

Before our electronic system leaves the ground, several problems need to be solved and tested.  Space radiation is one of the problems that are invisible at the ground level. The problem of single event upset will be addressed, its influence on FPGA architecture, modeling concepts, and methods of overcoming. The next section addresses the problem of power estimation in digital systems. The power consumption model construction will be shown and the implementation of the multiple clock domains system. The last section focuses on the ideas of algorithm mapping to hardware structures and efficient resource utilization. We will examine the resource sharing concept and its hardware effectiveness, building operation schedule, and its transformations for effective implementation. 

Using FPGAs for pre-silicon validation

Paweł Dowgiałło, INTEL

Every silicon development and fabrication is subject to the risk of major design defects resulting in a significant cost of fixing them. The risk gets higher with design complexity. High complexity increases time-to-market which, from an economical perspective, must be as small as possible to maximize commercial success. This trade-off is being addressed by companies in multiple ways, one type of recently most effective techniques is emulation and prototyping. In this area, FPGAs play a fundamental role thanks to their ability to implement and run silicon RTL with cycle-accuracy and within a relatively short time. The speech will cover the gains of applying FPGAs to address silicon validation risks, outline the process and highlight major difficulties and challenges. 

Hardware design performance insights at up & running FPGA

Andrzej Stasiak PhD, INTEL

There are many tools and methods to estimate and statically calculate the design performance before we move the RTL to FPGA. Once we implement the project and get an expected benchmark number via simulation/estimation, it seems the project is done. The problem may arise and become significant when our design due to internal / IO / other dynamics, does not meet set performance minimum threshold while runtime. The architecture/design itself then needs deep investigation while the runtime. This article discusses methods and techniques, including data collection and further offline analysis, to narrow down the design performance bottlenecks. 

Vendor Independent FPGA Implementation
for Safety-Critical Designs

Rakesh Jain, SIEMENS

Today’s designers have many choices – between ASIC/FPGA and multiple FPGA vendors, such as NanoXplore, Xilinx, Microchip and Intel. Siemens EDA has a complete FPGA vendor-independent flow from Catapult HLS, Precision FPGA Synthesis and FormalPro LEC/Questa verification. For safety-critical and high-reliability applications, Precision Hi-Rel offers industry’s most comprehensive SEE (Single Event Effects) mitigation strategies – TMR, safe FSM, ECC RAMs, etc., and, integration with provides assurance that synthesis-based mitigated design is functionally equivalent to the RTL, ensuring DO-254 certification. 

 

Integrated Workflows for Deploying
Deep Neural Networks on FPGAs

Dimitri Hamidi, MathWorks

Deep learning on FPGAs is playing an increasing role across a growing number of systems and applications due to FPGAs’ unique attributes of flexibility, high throughput, low latency, and per-watt performance. Nevertheless, the high development effort and the need for extensive hardware knowledge might become a prohibiting factor when targeting deep learning to FPGAs.  

This presentation illustrates an integrated workflow that simplifies the task of design exploration and prototyping of deep neural networks on FPGAs for control design, signal, and image processing applications.  

It connects algorithm, system, and hardware teams and enables early collaboration while accelerating the development process, both in the concept phase and in the implementation phase.  

The workflow is centered around a customizable deep learning processor with synthesizable RTL code generation support. Moreover, deployment for prototyping does not require specific hardware skills.  

Prior to deployment, the user can rapidly prototype the custom deep learning network and bitstream by visualizing intermediate layer activation results and verifying prediction accuracy without target hardware since the emulation is supported. Furthermore, performance and resource utilization can be pre-estimated and can be later confirmed with synthesis results and on-board profiling data after rapid deployment. The user can further fine-tune the performance to meet system constraints by redesigning the networks, fixed point quantization, and by trading off hardware resource usage with latency.  

The modular deep learning processor is portable, customizable and can be integrated into a reference design via AXI interfaces. Moreover, the integration process can be automated. 

We describe the architecture of this processor in detail and show how it can be customized and quickly deployed for deep learning inference on FPGA boards.   

The Space around us – You didn’t know that about smartphones

Tomasz Rożek PhD, Nauka To Lubię

Have you ever wondered what impact space technologies have on our everyday lives? When you answer the phone or fry eggs and bacon, you won’t even think that all this is possible thanks to discoveries made in super advanced laboratories. And at the beginning, these technologies were not invented to fry eggs … 

Many of the technologies that were created to explore the Cosmos are now used to improve life on the planet Earth. What would an average flat look like without them? A bit empty. Because we do not even realize how many of the advanced inventions that we use today to perform completely mundane activities. That’s why it’s so easy to amaze us with the information that baby diapers and a Gore-Tex jacket come from outer space. One of the most cosmic inventions are smartphones, without which most of us today cannot imagine life. If not for space missions, smartphones would probably not be there. The technologies used for their production come from space missions. 

FPGAs in Space Communication for Dummies

Michał Kuklewski, Thales Alenia Space

Due to their versatility and configurability, Field Programmable Gate Arrays (FPGAs) continue to be a very attractive choice in many places instead of purpose build ASICs. Space applications – in low or high orbit or even on other planets – are one of them. Depending on mission conditions or requirements, there is the possibility of using commercial off-the-shelf (COTS) devices in contrast to radiation-hardened FPGAs with built-in protection by technology. The use of any of these has associated implications and requires appropriate protection to assure reliability and achieve its function. 

As an example, the application is terminals for space communication – either between a ground station and a satellite or between satellites.  To achieve it, space agencies are following CCSDS standards, thus enabling the interconnection of different systems, while minimizing risks during missions, maximizing success rate and achieving interoperability. 

This presentation features a compilation of information from the ECSS standards and handbooks for protecting FPGAs against the effects of space radiation and an introductory description of CCSDS communication standards that allow communication with satellites. 

Mars – the most fascinating target for the space exploration
 – the technological challenge
 

Piotr Orleański DSc, CBK PAN Warszawa

The lecture will present the summary of the different space missions to Mars with the special attention on the technological challenges (environment conditions, available power, communication issues, components reliability). The more detailed information will be given on the three missions (Mars Express, ExoMars and InSight) where Polish engineers have been involved in design and manufacturing of the space instruments. 

Sending humans to Mars: a beginner’s guide

Jakub Hajkuś, To Jakiś Kosmos

So, you’re about to go to Mars? That’s great! Pack your toothbrush and lunch box. Your spacecraft isn’t ready? Oh, You don’t have one yet. Let’s try to do something about it. It’s not easy to get from Earth to Mars, but I’ll walk you through the process. Leaving our blue planet, cruising and landing on Mars require creativity. I will introduce you to a few options from which you can choose. Better clear your schedule as the journey usually takes several months. Warm clothes and sunscreen are a must. Being in space or on Mars can hardly be called a perfect holiday. I almost forgot! Consult with your doctor about whether you may be exposed to strong cosmic rays. Don’t worry, you are in good hands!

The Hitchhiker’s Guide to the FPGAs.
How to make FPGAs work in space

Adam Milik DSc, ALDEC

Before our electronic system leaves the ground, several problems need to be solved and tested.  Space radiation is one of the problems that are invisible at the ground level. The problem of single event upset will be addressed, its influence on FPGA architecture, modeling concepts, and methods of overcoming. The next section addresses the problem of power estimation in digital systems. The power consumption model construction will be shown and the implementation of the multiple clock domains system. The last section focuses on the ideas of algorithm mapping to hardware structures and efficient resource utilization. We will examine the resource sharing concept and its hardware effectiveness, building operation schedule, and its transformations for effective implementation. 

Using FPGAs for pre-silicon validation

Paweł Dowgiałło, INTEL

Every silicon development and fabrication is subject to the risk of major design defects resulting in a significant cost of fixing them. The risk gets higher with design complexity. High complexity increases time-to-market which, from an economical perspective, must be as small as possible to maximize commercial success. This trade-off is being addressed by companies in multiple ways, one type of recently most effective techniques is emulation and prototyping. In this area, FPGAs play a fundamental role thanks to their ability to implement and run silicon RTL with cycle-accuracy and within a relatively short time. The speech will cover the gains of applying FPGAs to address silicon validation risks, outline the process and highlight major difficulties and challenges. 

Hardware design performance insights at up & running FPGA

Andrzej Stasiak PhD, INTEL

There are many tools and methods to estimate and statically calculate the design performance before we move the RTL to FPGA. Once we implement the project and get an expected benchmark number via simulation/estimation, it seems the project is done. The problem may arise and become significant when our design due to internal / IO / other dynamics, does not meet set performance minimum threshold while runtime. The architecture/design itself then needs deep investigation while the runtime. This article discusses methods and techniques, including data collection and further offline analysis, to narrow down the design performance bottlenecks. 

Vendor Independent FPGA Implementation
for Safety-Critical Designs

Rakesh Jain, SIEMENS

Today’s designers have many choices – between ASIC/FPGA and multiple FPGA vendors, such as NanoXplore, Xilinx, Microchip and Intel. Siemens EDA has a complete FPGA vendor-independent flow from Catapult HLS, Precision FPGA Synthesis and FormalPro LEC/Questa verification. For safety-critical and high-reliability applications, Precision Hi-Rel offers industry’s most comprehensive SEE (Single Event Effects) mitigation strategies – TMR, safe FSM, ECC RAMs, etc., and, integration with provides assurance that synthesis-based mitigated design is functionally equivalent to the RTL, ensuring DO-254 certification. 

 

Integrated Workflows for Deploying
Deep Neural Networks on FPGAs

Dimitri Hamidi, MathWorks

Deep learning on FPGAs is playing an increasing role across a growing number of systems and applications due to FPGAs’ unique attributes of flexibility, high throughput, low latency, and per-watt performance. Nevertheless, the high development effort and the need for extensive hardware knowledge might become a prohibiting factor when targeting deep learning to FPGAs.  

This presentation illustrates an integrated workflow that simplifies the task of design exploration and prototyping of deep neural networks on FPGAs for control design, signal, and image processing applications.  

It connects algorithm, system, and hardware teams and enables early collaboration while accelerating the development process, both in the concept phase and in the implementation phase.  

The workflow is centered around a customizable deep learning processor with synthesizable RTL code generation support. Moreover, deployment for prototyping does not require specific hardware skills.  

Prior to deployment, the user can rapidly prototype the custom deep learning network and bitstream by visualizing intermediate layer activation results and verifying prediction accuracy without target hardware since the emulation is supported. Furthermore, performance and resource utilization can be pre-estimated and can be later confirmed with synthesis results and on-board profiling data after rapid deployment. The user can further fine-tune the performance to meet system constraints by redesigning the networks, fixed point quantization, and by trading off hardware resource usage with latency.  

The modular deep learning processor is portable, customizable and can be integrated into a reference design via AXI interfaces. Moreover, the integration process can be automated. 

We describe the architecture of this processor in detail and show how it can be customized and quickly deployed for deep learning inference on FPGA boards.   

The Space around us – You didn’t know that about smartphones

Tomasz Rożek PhD, Nauka To Lubię

Have you ever wondered what impact space technologies have on our everyday lives? When you answer the phone or fry eggs and bacon, you won’t even think that all this is possible thanks to discoveries made in super advanced laboratories. And at the beginning, these technologies were not invented to fry eggs … 

Many of the technologies that were created to explore the Cosmos are now used to improve life on the planet Earth. What would an average flat look like without them? A bit empty. Because we do not even realize how many of the advanced inventions that we use today to perform completely mundane activities. That’s why it’s so easy to amaze us with the information that baby diapers and a Gore-Tex jacket come from outer space. One of the most cosmic inventions are smartphones, without which most of us today cannot imagine life. If not for space missions, smartphones would probably not be there. The technologies used for their production come from space missions. 

Huge thanks to:

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