Coverage Driven Verification
Coverage driven verification – an introduction to a smart metric based verification approach
When do you know your design meets the requirements? What is coverage and why should we collect it? What is code coverage or functional coverage?
These are the type of questions that come to mind, when we think about coverage and verification. Before releasing a design to production we should be able to answer the question: “is my design verified”. In order to answer that question we need to understand the different ways that one can collect coverage and measure the readiness of the design – this presentation will give an introduction to different coverage metrics and how these can be applied to your daily design verification work.
Targeting Signal Processing Algorithms to Systems-on-FPGA
Signal processing engineers use MATLAB and Simulink at all stages of development – from analyzing signals and exploring algorithms to evaluating design implementation tradeoffs for building real-time signal processing systems. Beside of using filter algorithms and spectral analysis, in advanced signal processing systems also machine learning and deep learning methods are being used across different applications such as communications (including 5G), radar, audio and video, medical devices, and IoT.
State of the art FPGAs and System-on-Chip (SoC) FPGAs offer significant performance and flexibility for the implementation of such advanced signal processing systems. With MATLAB and Simulink these algorithms can be developed and validated, they can be refined and converted to fixed-point, and finally C and HDL code can be generated for the deployment on Systems-on-FPGA.
This presentation provides an overview of the workflows from signal processing algorithm design to implementation on FPGAs and SoC FPGAs. It goes more into depth on the fixed-point conversion and HDL code generation steps and highlights the prototyping and verification capabilities.
Refactoring SystemVerilog code
“Code refactoring” refers to changes of an existing source code without affecting its external behaviour. Code refactoring helps to keep the code readable and maintainable.
In this talk I will discuss the importance of refactoring in FPGA projects, the necessary conditions and expected results. I will show how some techniques taken from object-oriented world can be applied to synthesizable SystemVerilog code.
ASIC vs FPGA (Selection criteria, Compatibility, Porting challenges)
Rapid progress in digital chips development and shrinking process nodes to unbelievably small dimensions constantly open new doors for people wanting to touch on some areas of integrated circuits development. Given that modern chips can perform tasks never possible in the past, the interest in Hardware side of digital electronics is growing not only within electronics engineers but also software engineers quite bored by playing with 3rd party libraries and even non-technical enthusiasts and hobbyists who look for real fun and fulfilment in building functional design in real hardware regardless of it is complex processor with game-changing architecture or just simple diode pulsing controller (there is nothing that makes HW designer happier than blinking diode, right? J).
So you decided to design a piece of digital HW and then what? This lecture aims to shed some light on selection criteria with respect to the type of HW that is reasonable to choose depending on project scale, budget, destination and experience in designing.
The Mars Chronicle: FPGA Verification Platform Saves the Day
Vladislav Palfy, Director of Application Engineering at OneSpin
Whether you are developing an AI/ML accelerator, a 5G baseband chip demonstrator or a radiation-hardened controller for a satellite, design bugs, and security vulnerabilities can hit you hard. Who wants an asteroid damaging the ship?
As FPGA complexity arises and project time shrinks, automated, formal-based verification solutions provide a much-needed shield. Automatic formal checks can be effectively added to your continuous integration (CI) flow, detecting both simple and corner-case RTL bugs. Verification apps can take the pain out of many verification tasks, including reset and x-propagation verification, protocol verification, RISC-V core correctness proof, and coverage closure. What about flipping the hyperspace switch in your FPGA synthesis tool to get the speed you need? Formal equivalence checking for FPGA flows proves that nothing “funny” ends up in the netlist. Don’t get stuck in the lab or upset your customer.
Join this talk and see how to find design issues sooner and with low effort – before they become visible on anyone’s radar.
P4 and Intel PAC N3000 – make FPGA networking deployment faster
Mirosław Walukiewicz, Solution Architect in Intel
Implementing of own network pipelines in HW was a dream of many generations of developers.
Some time ago there was started at Stanford University an effort of defining HW independent language for programming network pipelines that can be easy converted into programmable HW containing parsers, Match-Action-tables and de-parsers.
The presentation presents a way how P4 could be converted into FPGA and how it simplifies the programming flow and enables usage of FPGA for developing many network pipelines defined by P4 language.
FPGA accelerators for compute: Intel PAC faster
Paweł Olejniczak, SoC design engineer in Intel
The portfolio of Intel® FPGA Programmable Acceleration Cards (Intel FPGA PACs) help you move, process, and store your data faster and more efficiently.
By providing hardware programmability on production qualified platforms, solution providers can design and then deploy the latest solutions quickly, while allowing for the flexibility needed in a rapidly changing environment.