“How to design FPGAs (in Clojure)”
Michał Kahl, Nokia
Over the last thirty years several attempts have been made to allow programmers to design FPGA code in functional programming languages, instead of traditional hardware description languages (Verilog, SystemVerilog and VHDL).
A new approach is presented, where Clojure syntax is used to write synthesizable code in a quest for simplicity. The code is translated to Verilog using an open source tool called Charbel.
“Fixing bugs early”
Daniel Aronsson, Mathworks
More than 80 percent of FPGA projects have non-trivial bugs that escape into production. How do we avoid that? How do we discover bugs early so that they can be fixed in time? Here we look at how a high-level model in Simulink performs bit-exact and cycle-exact simulations and allows us to verify early. When all bugs are eliminated, the model maps exactly to the FPGA, meaning that the VHDL can be generated completely automatically.
“Highlevel synthesis / CatapultC”
Esa-Matti Turtinen, Siemens
Catapult HLS (High-Level Synthesis) and C++-level design and verification are reducing entire project development times by half or more in today’s ASIC and FPGA designs. HLS is being used to create production-quality HW Accelerators for multiple applications such as 5G and Communication, Image and Video Processing, Automotive, and AI/ML much faster than hand-coded RTL with equivalent power, performance and area.
This presentation will give high-level technical overview of the Catapult HLS platform that you can use in your future projects to speed-up your development process.
“Automate hacking of your RTL code”
Maciej Wojtowicz, Nokia
While designing your design for FPGA, in many cases you struggle to have platform/technology independent RTL code that you could verify in simulation before loading it into FPGA project.
What is more, FPGA tools seldom support modern code editing IDE features so it is quite common that users write their RTL in other environments that natively in e.g. Vivado or Quartus.
To meet expectations of designs continuously getting more complex, the designers are looking for simple and highly automated design environments to boots their productivity.
The designers might maintain multiple digital designs out of which some could be commercial and the others open sourced. Of course, the convenience of having common design environment in these two cases would be extremally useful.
Is it possible to combine Free/Simple and highly automated design environment then?
Most of the people would likely answer: “Well, it is impossible at all… These three areas are simply in contrast which one another.”.
This statement is fair, however, how about thinking about some small reasonable trade-offs?
The goal of this talk to show the concept of “Free/Simple and highly automated design environment” with highlighting those trade-offs.
Let us convince you that “Free/Simple and highly automated design environment” is not only possible but not as difficult as you think!
The presentation is structured to be real fun for you! It covers very practical demo part, showing hacking RTL code on the fly (with crazy automation backends) and creating functional design from scratch (including its verification) in just few minutes.
Did you know that you can use Python code to verify your RTL?
Did you know that you can use RTL code to “draw” logic diagrams?
Did you know that you can use text editor as RTL debugger?
These questions and much more will be covered during the talk!
“Verilator – Open Source simulator”
Rafał Kozik, Nokia
Verilator provide quite unusual way of simulating Verilog. It converts its synthesizable part to C++ code. In speech I will show how to create testbench for simple project and automate it on Gitlab.
“Logic Synthesis and Verification made simple”
Adam Milik, Aldec
The presentation will present the issues of synthesis illustrating the differences in the behavior of the HDL model and the system obtained after logical synthesis.
We will also devote some time to the layout verification process.
“Automatic Formal Checking“
Neil Rattray, Siemens
Whether you are developing an AI/ML accelerator, a 5G baseband chip demonstrator, or a radiation-hardened controller for a satellite, design bugs and security vulnerabilities can hit you hard.
As FPGA complexity arises and project time shrinks, automated, formal-based verification solutions provide a much-needed shield.
Automatic formal checks can be effectively added to your continuous integration (CI) flow, detecting both simple and corner-case RTL bugs without having to write testbenches. Verification apps can take the pain out of many verification tasks, including reset and x-propagation verification, protocol verification, RISC-V core correctness proof, and coverage closure.
Formal equivalence checking for FPGA flows proves that nothing “funny” ends up in the netlist. Don’t get stuck in the lab or upset your customer. Join this session and see how to find design issues sooner and with low effort.