Applying Formal Technologies to FPGA Verification

Juho Järvinen

According to a recent 3rd party survey, some 84% of FPGA-based design projects have non-trivial bugs that escape into production.

As FPGAs are becoming more complex – and the cost of bug escapes becoming higher – more Design & Verification engineers are turning to exhaustive formal analysis to address verification challenges that are difficult and time consuming to do with simulation, but can be quickly and exhaustively handled by formal.

In this talk we will give a brief primer on what formal analysis is, and how it is now available in easy-to-use apps that require no prior knowledge of assertion-based verification or formal methods. These formal apps combine automated, exhaustive formal analysis under-the-hood with well-documented methodologies focusing on specific, high-value verification challenges that are poorly served by other technologies. We will share specific examples in the context of critical design and verification tasks like clock and reset domain crossing analysis, dead code detection, code coverage closure, secure path integrity analysis, and interface and arbitration logic verification.

Targeting Signal Processing Algorithms to Systems-on-FPGA

Werner Bachhuber

No abstract yet. It will be here soon 🙂

Refactoring SystemVerilog code

Michał Kahl

No abstract yet. It will be here soon 🙂

Programming Pearls on FPGA: Implementing Linear Scan for Pulse Detection

Aleksander Łoś

No abstract yet. It will be here soon 🙂

Verifying Functional Correctness, Security and Trust in FPGA Designs

Vladislav Palfy

Today’s FPGA designs are large and complex, often qualifying as system-on-chip (SoC) devices. This has raised the bar for verification of FPGA designs; trying to debug in the bring-up lab is no longer practical. Many verification steps can be automated to reduce time and effort. This talk covers the use of automatic checks to detect a wide range of design issues, including security risks, and the use of equivalence checking to find errors and trust violations in the FPGA implementation flow.